1. Field of the Invention
The present invention is directed generally to a programmable controller, which incorporates a sequence control program, for inputting and outputting information to a variety of local intelligent appliances in an FA (Factory Automation) field for controlling factory production lines or in a PA (Process Automation) field for controlling multiple industrial processes.
The present invention is directed more particularly to an improvement of a change-over system associated with a 1-bit processor and an ordinary processor for executing the sequence control program. The present invention also improves the ability of a user to specify particularly a BASIC program associated with communication with a connected host computer system; the ability to control a group of input/output (I/O) cards for transferring signals to and receiving signals from the local appliances; and the ability to program the sequence control program installed inside the programmable controller.
2. Description of the Prior Art
In general, a central processing unit (CPU) board in a programmable controller is equipped with a typical general purpose processor (e.g., a 16-bit microprocessor such as a Motorola 68000 or the like) serving as a first processor, and a dedicated processor for executing only arithmetic operations or logic (e.g., a math co-processor such as from the Motorola 68000 family or the like), which serves as a second processor. These processors are alternately placed in operation in accordance with a sequence control program stored in a program memory.
FIG. 1 illustrates an example of a module in which the first and second processors operate alternately to read from the single program memory.
In the module depicted in FIG. 1, a first processor CPU 1, typically a general purpose processor (e.g., a 16-bit Motorola 68000 microprocessor), and a second processor BPU (bit processor unit) 2, used as a dedicated processor for executing arithmetic operations or logic (e.g., a math co-processor from the Motorola 68000 family), are connected via an information bus b to a program memory 3. Second processor BPU 2 is sometimes referred to as a 1-bit processor.
Program memory 3 stores machine language commands as program commands for processor CPU 1. Processor CPU 1 executes processing by sequentially reading the machine language commands. When commands read from program memory 3 are to be executed by processor BPU 2, processor CPU 1 transmits the instructions and data to processor BPU 2. Subsequently, the commands read from program memory 3 are sequentially issued to processor BPU 2 to await execution when processor BPU 2 acquires an execution control right.
A disadvantage of this type of prior art programmable controller is that, by utilizing a combination of processors CPU 1 and BPU 2, the system must be designed so that the machine language commands stored in program memory 3 can be allocated to both processors CPU 1 and BPU 2 before the commands can be executed, rather than allocating the commands only to the processor desired for execution.
Other recent prior art designs often utilize interpretive language commands (commands that must be interpreted before they may be executed) designed independently of the machine language commands for processor CPU 1, usually storing these interpretive language commands in program memory 3.
An apparatus making use of interpretive language commands and machine language commands is capable of arbitrarily storing commands to be executed by processor BPU 2 together with commands to be executed by processor CPU 1. There is no need to design the system so that the commands are allocated to both CPU 1 and BPU 2. Instead, processor CPU 1 or BPU 2 is specified in conformity with the contents of the commands read from program memory 3, and it is therefore possible to increase practical efficiency and expand the commands to be executed by the processor BPU 2.
However, there is a disadvantage in employing both machine language commands and interpretive language commands. When BPU 2 operates, processor CPU 1 must sequentially read the program commands from program memory 3 and supply these commands to BPU 2, which results in a time-consuming transfer of the program commands.
There is also a disadvantage when only interpretive language commands are used. Processor CPU 1 must interpret all the commands read from program memory 3 and determine which processor to use for execution of each command. Especially in an apparatus where the operations of processors CPU 1 and BPU 2 are frequently alternated, an excessive delay in processing occurs.